A problem encountered in the design of buried-channel CCD's to operate with 0-5 volt clock signals is the design of an output stage which can also be operated from the standard 5-volt power supply, so one can avoid the need for a high voltage supply. The problem arises due to the offset between in-channel potentials in the buried-channel and the gate potentials applied to the gate electrodes of these devices to induce these in-channel potentials. Consider a fabrication process using n-type charge transfer channels buried in a p-type silicon substrate. Two-phase clocking is used with each two-phase gate electrode structure consisting of a first-polysilicon-layer gate electrode preceded by a second-polysilicon-layer gate electrode receptive of the same gate electrode potential. This induces a two-step staircase potential profile under each two-phase gate electrode structure that facilitates charge transfer only in a forward direction. The in-channel potentials under the first-polysilicon-layer gate electrodes tend to be five or six volts more positive than the gate electrode potentials inducing them. If one uses 0-5 volt clock voltages on the gate electrodes of the buried-channel CCD, and follows the CCD with a floating-diffusion electrometer in which the floating diffusion is periodically reset to 5 volts, signal charge that has been transferred under the floating diffusion will tend to flow back under that gate electrode, as the clocking voltage applied to the first-polysilicon-layer gate electrode immediately preceding the floating diffusion goes positive. This back flow of charge causes a non-linear reduction in the signal voltage developed on the floating diffusion, which effect is undesirable.
Deriving higher reset drain voltages from the 5 volt supply, using voltage-doubling or voltage-tripling techniques, is an unattractive solution to this problem. If the reset drain voltage is increased, the drain voltages on the field effect transistor used in the electrometer and the source follower thereafter have to be increased also. The current demands of the field effect transistors require capacitor sizes in the doubler or tripler that are, practically speaking, too large to be integrated on the same semiconductor substrate as the burried channel CCD.